Tech Files

Semiconductor device designers are continuously looking for ways to maximise the number of nodes that fit into each area of semiconducting wafers. CMP processing of 3D stacked logic devices in the form of finFETs and 3D memory can prove more difficult to process than planar ICs. Many more steps are required throughout the process.

Silicon-based semiconducting integrated circuits have changed the world immeasurably over the past 50 years. Today the number of silicon chips in use far outweighs the number of humans currently alive.

In recent years, diamond has emerged as not only a girl’s best friend, but also as contender as an engineer’s best friend – if the technical challenges of exploiting its remarkable properties can be overcome.

The wafers used to make semiconducting chips for electronic devices all have one thing in common – they need to be smooth – super smooth.

According to the Semiconductor Industry Association (SIA), worldwide sales of semiconductors reached $84 billion during the second quarter of 2015 – an increase of 1.0% over the previous quarter.

For many years, the wafer finishing process has been subject to an element of manual monitoring and control. With a typical wafer lapping and polishing cycle taking around an hour of conditioning to complete, the level of manual monitoring required is a drain on resource and efficiency.

The electronic materials industry is changing, with process complexity driving growth in the slurries and pads used in chemical-mechanical polishing (CMP) processes.

Almost everywhere you looked at Semicon West in San Francisco this year, semiconductor manufacturers were discussing the increased complexity of the products they are now designing.