Application Process Notes

Logitech know how.

We have developed a wide range of  application notes in order for you to gain a deeper understanding of the technologies involved in working with certain materials and applications.

Each application note details process requirements, methodologies and system specifications required in order to process a sample to its optimum geometric control.

Geological Thin Section Preparation: LP70

Leader in geological Thin Section Preparation and high-throughput system for R&D and production. Download “Thin Section Preparation” for application details, specifications, and results.

4” GaAs Wafer Backthinning

GaAs wafers excel in high-frequency and optoelectronics. Download the application note for methods to achieve optimal precision on 4″ wafers.

Polishing Fibre Arrays

Logitech offers methods for thinning fusion-bonded wafers to 10μm. Download “Fused Wafers” to learn about process routes, bonding techniques, and automated thinning and polishing.

Processing III-V Semiconductors: Indium Phosphide

Discover the processes for preparing Indium Phosphide (InP) wafers, used in high-power electronics like fibre optics and laser diodes. InP wafers are lapped and CMP polished to meet surface specifications for device fabrication.
PM6 Lapping machine

Advances in Indium Phosphide Processing: PM6

Learn how the Logitech PM6 enhances Indium Phosphide (InP) processing with precise lapping and CMP polishing. Download the application note for techniques, process steps, and parameters to achieve Ra 1-2nm and TTV <3µm on 3″ InP wafers.

Silicon Carbide, Sapphire & Gallium Nitride
Substrate Preparation

Learn how Silicon Carbide, Sapphire, and Gallium Nitride substrates improve semiconductor production. Download the application note for process details, including faster cycle times and precise control with the PM6 Lapping & Polishing System.

GaAs Wafer Processing: LP70

Discover how Logitech’s automated lapping and polishing solutions boost productivity and repeatability by 40%, reducing user expertise requirements and minimizing wafer damage while cutting operating costs