Polishing up after Semicon West
24th July 2015
Almost everywhere you looked at Semicon West in San Francisco this year, semiconductor manufacturers were discussing the increased complexity of the products they are now designing.
Chip complexity is growing because engineers are looking for ways to compensate for the laws of physics that are impeding the path of Moore’s law. For those in need of a recap, Gordon Moore, co-founder of Intel, predicted in 1965 that the number of transistors in a dense integrated circuit would double approximately every two years.
Whether that complexity lies in the vertical axis with transistors being stacked vertically upon each other, or in the need for heterogenous integration of technologies in a single package.
No matter the direction of travel, the fact is that chips are getting more complex, and that makes the wafers they are made from increasingly valuable.
It is therefore increasingly important that the fate of these wafers is not left to lapping and polishing processes and technology that involve a significant level of user expertise, guesswork and development time.
It is a very skilled job to achieve the surface finish required in demanding wafer applications. These processes are also time consuming and not conducive to the productivity levels demanded by industry. After all, the search for cost reduction in semiconductor device production is driven by volume and yield.
Automated systems can remove this variability and help increase productivity, to learn more, download our latest whitepaper.
